PC sampling oscillograph for subnanosecond time region

8 November 1990

journal article
Published by Institution of Engineering and Technology (IET) in Electronics Letters

Vol. 26 (23) , 1950-1952
https://doi.org/10.1049/el:19901262

Abstract

A new approach to a voltage controlled delay circuit for the subnanosecond regime based on a nonlinear lumped network with varicaps is presented. Its application in a PC controlled sampling oscillograph and results achieved with an experimental function model are described.

Keywords

VARICAPS
VOLTAGE CONTROLLED DELAY CIRCUIT
PC CONTROLLED SAMPLING OSCILLOGRAPH
NONLINEAR LUMPED NETWORK
A/D CONVERTORS
SUBNANOSECOND TIME REGION
EXPERIMENTAL FUNCTION MODEL

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