A 60 GHz PLL synthesizer with an injection locked frequency divider using a fast VCO frequency calibration algorithm
- 1 December 2012
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 21654727,p. 646-648
- https://doi.org/10.1109/apmc.2012.6421690
Abstract
A 60 GHz phase-locked loop (PLL) synthesizer with an injection locked frequency divider (ILFD) is presented. The PLL employs a simple and fast calibration algorithm consisting of the VCO sub-band selection and the adjustment of the ILFD locking range. The proposed PLL is demonstrated using 90 nm CMOS. The calibration process converges within 100 μsec at all 4-channels defined by the Wireless Gigabit Alliance (WiGig).Keywords
This publication has 2 references indexed in Scilit:
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