Design of High-Speed Digital Divider Units

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Abstract
The division operation has proved to be a much more difficult function to generate efficiently than the other elementary arithmetic operations. This is due primarily to the need to test the result of one iteration before proceeding to the next. The technique described in this contribution reduces the iteration time by the use of a redundant quotient representation, which avoids the need to complete the arithmetic operation. A borrow–save subtractor (analogous to a carry–save adder) can then be used for the arithmetic. Further improvement is obtained by use of a lookahead decoding technique. Cost reductions are obtained either by use of uncommitted logic arrays, or by a novel borrow–save system using commercially available adder circuitry. A comparison of a number of divider units with a wide range of cost and speed is included.

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