Efficient FPGA implementation of Gaussian noise generator for communication channel emulation

11 November 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

Vol. 1, 366-369
https://doi.org/10.1109/icecs.2000.911557

Abstract

In this paper, a high accuracy Gaussian noise generator emulator is defined and optimized for hardware implementation on a FPGA. The proposed emulator is based on the Box-Muller method implemented by using ROM tabulation and a random memory access. By means of accumulations, the central limit method is applied to the Box-Muller output Gaussian distribution. After presenting the algorithmic method, this paper analyzes its efficiency for different noise signal formats. Then the architecture to fit into a FPGA is explained. Finally, results from the FPGA synthesis are given to show the value of this method for FPGA implementation.

Keywords

FIELD PROGRAMMABLE GATE ARRAYS
GAUSSIAN NOISE
COMMUNICATION CHANNELS
EMULATION
AWGN
HARDWARE
READ ONLY MEMORY
GAUSSIAN DISTRIBUTION
ALGORITHM DESIGN AND ANALYSIS
ADDITIVE WHITE NOISE

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