A 2 mA/3 V 71 MHz IF amplifier in 0.4 μm CMOS programmable over 80 dB range

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Abstract
Passive filters account for a significant part of the cost in component price and space, in a wireless telephone handset. To reduce the number of passive filters, recent highly integrated transceiver ICs tend to use single-conversion superhet architecture. The majority of the system gain in those transceivers are realized either at the IF frequency or at baseband. The baseband approach has the advantage of lower power consumption. A high gain IF amplifier, on the other hand, prevents offset and flicker noise from significantly degrading the signal. This IF amplifier is programmable from -20 dB to 60 dB in 2 dB steps. The amplifier is part of a CMOS RF transceiver IC. One of the challenges for this design is high gain at relatively high frequency, with associated stability problems. For the GSM handset, low power is a strong requirement. CMOS implementation involves additional design considerations. To minimize power consumption, the IF amplifier is realized as a chain of three amplifiers of the same configuration, so each amplifier's unity gain bandwidth is limited to around 700 MHz. The amplifier, with gain-programming logic, is fabricated in a 0.4 /spl mu/m CMOS process.

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