Considerations for the design of an SRAM with SOI technology

Abstract
A silicon-on-insulator process that has a thin silicon film and source/drain junctions driven to the underlying insulator and that provides significant advantages for fabrication of an SRAM for space applications, is presented. The advantages result primarily from a reduced collection volume for upset from an ionizing particle and the possibility of fitting larger devices in a memory-cell area limited by interconnection pitch. The reduced junction capacitance would also give an SRAM fabricated with such a process an advantage for the general high-performance SRAM market.

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