The system logic and usage recorder
- 1 January 1969
- proceedings article
- Published by Association for Computing Machinery (ACM)
- p. 219-229
- https://doi.org/10.1145/1478559.1478585
Abstract
A fundamental problem in monitoring the performance of a system with a hardware device is too much data. Inside the System/360 Model 40, for example, seventeen address bits and sixteen data bits may be processed every 2.5 microseconds; this rate is equivalent in bulk to about three novels per second but not generally equivalent in interest or information. The design objective for any hardware monitor, therefore, is to reduce the data it sees as soon as possible.This publication has 0 references indexed in Scilit: