An approach to symbolic timing verification
- 2 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 410-413
- https://doi.org/10.1109/dac.1992.227769
Abstract
Symbolic timing verij?cation is a powerful extension to traditional constraint checking that allows delays and constraints to be expressed as symbolic variables. In this paper, we present an approach to symbolic timing verification using constraint logic programming techniques. The techniques are quite powerjul in that they yield not only simple bounds on delays but also relate the delays in linear inequalities so that tra&oj% are apparent. We model circuits as communicating processes and our current implementation can verify a large class of mixed synchronous and asynchronous specijcations. The utility of the approach is illustrated with some examples.Keywords
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