Techniques to Reduce the Inherent Limitations of Fully Digit On-Line Arithmetic

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Abstract
A fully digit on-line arithmetic unit generates at least the i most (least) significant digits of the output after having been supplied no more than the (i + k) most (least) significant digits of each input, where k is some small constant. This digit serial property can be used to reduce the aggregate fill and flush times of a chained list of digit on-line arithmetic units (which in turn reduces the required amount of parallelism needed to obtain high hardware utilization), and the VLSI interconnection complexity (which in turn reduces pin count). However, because of this digit serial property, unique limitations may be imposed on any arithmetic unit which performs certain operations in a digit on-line manner. Furthermore, these limitations are inherent in the sense that any fully digit on-line arithmetic unit which performs these operations will have some type of similar limitations. For some calculations, these limitations may be so severe as to make evaluation of that calculation by a digit on-line arithmetic unit virtually impossible. For other calculations, these limitations may not be nearly as severe. We will investigate techniques to either avoid or reduce the impact of these limitations.

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