Verifying the summit bus converter protocols with symbolic model checking
- 1 February 1994
- journal article
- Published by Springer Nature in Formal Methods in System Design
- Vol. 4 (2) , 83-97
- https://doi.org/10.1007/bf01384079
Abstract
No abstract availableKeywords
This publication has 5 references indexed in Scilit:
- Symbolic model checking: 10/sup 20/ states and beyondPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Sequential circuit verification using symbolic model checkingPublished by Association for Computing Machinery (ACM) ,1990
- Automatic Verification of Sequential Circuits Using Temporal LogicIEEE Transactions on Computers, 1986
- Graph-Based Algorithms for Boolean Function ManipulationIEEE Transactions on Computers, 1986
- Automatic verification of finite-state concurrent systems using temporal logic specificationsACM Transactions on Programming Languages and Systems, 1986