Two-layer model for source resistance in selectively doped heterojunction transistors

Abstract
Selectively doped heterojunction transistors (SDHT's) for high-speed circuits require very low parasitic resistance. The standard one-layer model used to characterize GaAs FET's is shown by experiment to be inadequate for SDHT's, and a two-layer model of parasitic resistance is introduced. Parameters are measured for present devices, and it is demonstrated that a heavily doped GaAs cap can reduce SDHT parasitic source resistance by 50 percent at T = 300 K. The effectiveness of various strategies for further improvement is also assessed.