CMOS pipelined ADC employing dither to improve linearity

20 January 2003

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 109-112
https://doi.org/10.1109/cicc.1999.777253

Abstract

This paper presents a new method for applying linearity improving dither to a pipelined ADC employing digital error correction. This dither energy remains internal to the converter, only causing correctable errors in the internal uncorrected digital data stream. Unlike adding dither to the input signal, this new dither method does not consume signal bandwidth or dynamic range. Spurious free dynamic range improvements of 15 dB have been realized.

Keywords

LINEARITY
DYNAMIC RANGE
BANDWIDTH
ERROR CORRECTION
SOFTWARE RADIO
ANALOG-DIGITAL CONVERSION
NOISE REDUCTION
SIGNAL TO NOISE RATIO
SAMPLING METHODS
PIPELINES

This publication has 1 reference indexed in Scilit:

A 10-b 20-Msample/s analog-to-digital converter
IEEE Journal of Solid-State Circuits, 1992