ACE: A Circuit Extractor
- 1 January 1983
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 0738100X,p. 721-725
- https://doi.org/10.1109/dac.1983.1585736
Abstract
This paper describes the design, implementation and performance of a flat edge-based circuit extractor for NMOS circuits. The extractor is able to work on large and complex designs, it can handle arbitrary geometry, and outputs a comprehensive wirelist. Measurements show that the run time of the edge-based algorithm used is linear in size of the circuit, with low implementation overheads. The extractor is capable of analyzing a circuit with 20,000 transistors in less than 30 minutes of CPU time on a VAX 11/780. The high performance of the extractor has changed the role that a circuit extractor played in the design process, as it is now possible to extract a chip a number of times during the same session.Keywords
This publication has 1 reference indexed in Scilit:
- A Hardware Assisted Design Rule Check ArchitecturePublished by Institute of Electrical and Electronics Engineers (IEEE) ,1982