A fully operational 1-kbit HEMT static RAM

1 May 1986

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices

Vol. 33 (5) , 548-553
https://doi.org/10.1109/T-ED.1986.22531

Abstract

In this paper we describe the current status of materials and fabrication technologies, and optimal design of a memory cell, and the performance of fully functional 1-kbit HEMT SRAM's. The surface defect density on MBE-grown wafers has been reduced to less than 100 cm-2by improving MBE technology. Standard deviations of threshold voltages are 6.7 and 11.8 mV for enhancement-type and depletion-type HEMT's, respectively, measured in a 10 mm × 10 mm area. These deviations are sufficiently small for DCFL circuits. Memory cell design parameters have been optimized by circuit simulation, where the effects of variations in threshold voltages are taken into account. Full function of 1-kbit SRAM's has been confirmed by marching tests and partial galloping tests. The RAM chips have also shown excellent uniformity in access time. The difference between maximum and average values on the RAM chip is 4 percent.

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