A low-noise 1.6-GHz CMOS PLL with on-chip loop filter
- 22 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 407-410
- https://doi.org/10.1109/cicc.1997.606655
Abstract
A 1.6 GHz PLL has been fabricated in a 0.6 /spl mu/m CMOS technology. The PLL consists of an LC-tank circuit, divider, phase detector with charge pump and an on-chip passive loop filter. The VCO exhibits -105 dBc/Hz phase noise at a 200 kHz offset from the carrier. It occupies an active area of 1.5 mm/sup 2/ and dissipates 90 mW from a single 3 V supply.Keywords
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