A 200 Mb/s PRML read/write channel IC
- 23 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
The hard disk drive industry is looking at synchronous design techniques (PRML) with a view to increasing storage density. Currently the high performance commercial read/write channels use (0, 4/4) codes to achieve up to 120 Mb/s data transfer rates. This paper describes a fully integrated read/write channel IC that operates at over 200 Mb/s. The single-chip solution in 0.51 /spl mu/m BiCMOS, has 20 mm/sup 2/ die and uses 0.85 W at 200 Mb/s.Keywords
This publication has 3 references indexed in Scilit:
- A 72 Mb/s PRML disk-drive channel chip with an analog sampled-data signal processorPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A 16 MB/s PRML read/write data channelPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A 50 MHz eight-tap adaptive equalizer for partial-response channelsIEEE Journal of Solid-State Circuits, 1995