Hierarchical circuit verification

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Abstract
One of the crucial steps in designing VLSI circuits is to verify the correctness of the layout of the circuitry. Traditionally, this verification step is done by first flattering out the circuit hierarchy. This approach requires a substantial amount of computational overhead even for circuits that are relatively small. In this paper, a connectivity verification algorithm which exploits circuit hierarchy is presented. This algorithm works most efficiently with big circuits and is therefore useful for verifying VLSI circuits.

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