A Programmable 512 GOPS Stream Processor for Signal, Image, and Video Processing

1 February 2007

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 272-602
https://doi.org/10.1109/isscc.2007.373399

Abstract

A 34M transistor stream processor SoC for signal, image, and video processing contains 80 parallel integer ALUs organized into 16 data-parallel lanes with a 5-ALU VLIW per lane, two CPU cores and I/Os. Implemented in a 0.13mum CMOS technology, sixteen 800MHz data-parallel lanes combine to deliver performance of 512 8b GOPS or 256 16b GOPS.

Keywords

STREAMING MEDIA
SIGNAL PROCESSING
KERNEL
VLIW
DIGITAL SIGNAL PROCESSING
SWITCHES
REGISTERS
COMPUTER ARCHITECTURE
SIGNAL PROCESSING ALGORITHMS
BANDWIDTH

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Published by Institute of Electrical and Electronics Engineers (IEEE) ,2005
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A bandwidth-efficient architecture for media processing
Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002