A tutorial on built-in self-test. 2. Applications

1 June 1993

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Design & Test of Computers

Vol. 10 (2) , 69-77
https://doi.org/10.1109/54.211530

Abstract

For pt.1 see ibid., vol.10, no.1, p.73-82 (1993). The hardware structures and tools used to implement built-in self-test (BIST) pattern generation and response analysis concepts are reviewed. The authors describe testing approaches for general and structured logic, including ROMs, RAMs, and PLAs. They illustrate BIST techniques with real-world examples.

Keywords

TUTORIAL
BUILT-IN SELF-TEST
CIRCUIT TESTING
LOGIC TESTING
HARDWARE
CLOCKS
SHIFT REGISTERS
READ ONLY MEMORY
TEST PATTERN GENERATORS
AUTOMATIC TESTING

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