Simulation of the effects of grain structure and grain growth on electromigration and the reliability of interconnects

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Abstract
Electromigration-induced failure of on-chip interconnects continues to be a problem for the microelectronics industry. The electromigration failure rate of a population of similar lines is sensitive to statistical variation in the microstructural characteristics from line to line. These microstructural details depend upon the process and thermal history of the line as well as on the feature size (line length and width). Moreover, as the widths of interconnect lines have fallen below the median grain size of the films from which they are patterned, two distinct types of failure mechanisms have been observed. Determining which failure mechanism(s) will be observed, and in what proportion, is a crucial concern of reliability engineers. This article investigates the complex dependence of the dominant failure mechanism and overall reliability on process history, minimum feature size, line type, line microstructure, and line test conditions. A grain growth simulator has been used to model the microstructural evolution of a film during processing, both prior to and after patterning. In this fashion, large populations of lines with realistic microstructures have been generated in order to observe statistical differences in microstructure and failure rate. An electromigration model is then used to calculate stress evolution. By assuming a critical stress at which the line fails, the failure distributions and overall reliability of the interconnects are obtained, and the conditions under which a transition-in-failure mechanism will occur are predicted.