A 156 Mbps CMOS clock recovery circuit for burst-mode transmission
- 23 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
This paper describes a new timing circuit design technique for asynchronous burst-mode data transmission, such as Fiber To The Home (FTTH). Without external reference clock signals, it enables the quick extraction of clock signal from received NRZ data packets using a "gating timing circuit" and "burst PLL". The circuit's simple configuration reduces both size and power. A fabricated 0.5-/spl mu/m CMOS IC exhibits instantaneous response within one bit for 156 Mbps asynchronous data packets.Keywords
This publication has 2 references indexed in Scilit:
- High-speed, burst-mode, packet-capable optical receiver and instantaneous clock recovery for optical bus operationJournal of Lightwave Technology, 1994
- A 660 Mb/s CMOS clock recovery circuit with instantaneous locking for NRZ data and burst-mode transmissionPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1993