A 50-mW/ch 2.5-Gb/s/ch data recovery circuit for the SFI-5 interface using novel eye-tracking method

1 March 2004

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 57-60
https://doi.org/10.1109/vlsic.2003.1221160

Abstract

We developed a 2.5-Gb/s/ch digital data recovery (DR) circuit for the SFI-5 interface. Our unique approach of treating a sequential 16-bit incoming data as one unit achieved a fully digital "eye-tracking" DR circuit. Fabricated by 0.18-/spl mu/m SiGe-BiCMOS technology, the area of the DR circuit is 0.02-mm/sup 2//ch and its power consumption is 50 mW/ch at 1.8 V. The measured jitter tolerance at 2.5 Gb/s is 0.7 UI p-p, which satisfies the jitter specifications for the SFI-5.

Keywords

CIRCUITS
CLOCKS
JITTER
ENERGY CONSUMPTION
TIMING
LABORATORIES
AREA MEASUREMENT
POWER MEASUREMENT
OPTICAL BUFFERING
OPTICAL DEVICES

This publication has 0 references indexed in Scilit: