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The reduction of LSI chip costs by optimizing the alignment yields
Home
Publications
The reduction of LSI chip costs by optimizing the alignment yields
The reduction of LSI chip costs by optimizing the alignment yields
WL
W.T. Lynch
W.T. Lynch
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1 January 1977
proceedings article
Published by
Institute of Electrical and Electronics Engineers (IEEE)
https://doi.org/10.1109/iedm.1977.189140
Abstract
No abstract available
Keywords
ALIGNMENT YIELDS
REDUCTION OF LSI
LSI CHIP COSTS
OPTIMIZING THE ALIGNMENT
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Cited by 5 articles
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