On simulating faults in parallel

6 January 2003

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 110-115
https://doi.org/10.1109/ftcs.1988.5307

Abstract

Hardware engines (e.g. YSE and EVE) have been built to perform functional simulation of large designs over many patterns. The authors present a method of simulating faults in parallel that is applicable to these hardware simulation engines (and to software simulators with similar characteristics). A notion of independence between faults is used to determine the faults that can be simulated in parallel. An efficient algorithm is developed to determine the independent subsets of faults. Results of applying the algorithm to large examples are presented and shown to be very good by comparing them with theoretical lower bounds. This technique makes it feasible to fault simulate large networks using these hardware simulation engines.

Keywords

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