High Performance Mesfet Technology for GaAs ICs using Shallow n-Channels

1 November 1985

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 041-044
https://doi.org/10.1109/gaas.1985.10399508

Abstract

A comprehensive experimental study on GaAs MESFETs design principle has been made. With the fabrication process for WSi x - gate self-aligned MESFETs, performance has been improved by a factor of 2 through reduction of implant energy from 75 to 40 keV. Transconductance coefficients, K, as high as 2 mA/V ² for EFETs and 1.2 mA/V ² for DFETs have been attained at 1 µm gate length and 10 µm channel width, which are one of the highest ever reported. Consistent, fundamental data on K values and gate capacitance have been obtained. High performance MESFETs have been used successfully in a 4-Kb GaAs SRAM experiment.

Keywords

LOGIC GATES
MESFETS
GALLIUM ARSENIDE
THRESHOLD VOLTAGE
INTEGRATED CIRCUITS
IMPLANTS
RANDOM ACCESS MEMORY

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