A 6.2 ns 64Kb CMOS RAM with ECL interfaces

Publisher Website

1 January 1988

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 19-20
https://doi.org/10.1109/vlsic.1988.1037404

Abstract

No abstract available

This publication has 3 references indexed in Scilit:

Fast CMOS ECL receivers with 100-mV worst-case sensitivity
IEEE Journal of Solid-State Circuits, 1988
A 15-ns CMOS 64K RAM
IEEE Journal of Solid-State Circuits, 1986
Stability and SER analysis of static RAM cells
IEEE Transactions on Electron Devices, 1985