Design of a 2 × 2 fault-tolerant switching element
- 1 April 1982
- journal article
- Published by Association for Computing Machinery (ACM) in ACM SIGARCH Computer Architecture News
- Vol. 10 (3) , 181-189
- https://doi.org/10.1145/1067649.801726
Abstract
This paper describes the architecture of a 2 × 2 fault-tolerant switching element which can be used to modularly construct interconnection networks for multi-processing and local computer networking. The switching element uses distributed control and circuit switching. Its good gate-to-pin ratio can facilitate VLSI implementation.Keywords
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