A complete monolithic sample/hold amplifier
- 1 December 1974
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 9 (6) , 381-387
- https://doi.org/10.1109/JSSC.1974.1050531
Abstract
A monolithic sample/hold amplifier is described which includes the holding capacitor on the chip. System design considerations and tradeoffs are discussed, as well as the circuit design details. High performance is achieved by the use of a process which produces bipolar transistors and p-channel silicon-gate FET's (SIGFET's) on the same chip. Performance characteristics obtained include an acquisition time of 10 /spl mu/s (20-V step), an aperture delay time of 80 ns, and a droop rate of 30 mV/s.Keywords
This publication has 3 references indexed in Scilit:
- Recent advances in monolithic operational amplifier designIEEE Transactions on Circuits and Systems, 1974
- An improved performance MOS/bipolar op-ampPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1974
- A self-compensated monolithic operational amplifier with low input current and high slew ratePublished by Institute of Electrical and Electronics Engineers (IEEE) ,1969