Realizing biological spiking network models in a configurable wafer-scale hardware system
- 1 June 2008
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 21614393,p. 969-976
- https://doi.org/10.1109/ijcnn.2008.4633916
Abstract
An analog VLSI hardware architecture for the distributed simulation of large-scale spiking neural networks has been developed. Several hundred integrated computing nodes, each hosting up to 512 neurons, will be interconnected and operated on un-cut silicon wafers. The electro-technical aspects and the details of the hardware implementation are covered in a separate contribution to this conference. This paper focuses on the usability of the system by demonstrating that biologically relevant network models can in fact be mapped to this system. Different network configurations are established on the hardware by programmable switch matrices, repeaters, and address decoders. Systematic routing algorithms are presented to map a given network model to the hardware system. Routing is simulated for several network examples, proving the systempsilas practical applicability. Furthermore, the routing simulations are used to fix values for yet open hardware parameters.Keywords
This publication has 4 references indexed in Scilit:
- Emergence of population synchrony in a layered network of the cat visual cortexNeurocomputing, 2007
- Parallel network simulations with NEURONJournal of Computational Neuroscience, 2006
- A Quantitative Map of the Circuit of Cat Primary Visual CortexJournal of Neuroscience, 2004
- An egalitarian network model for the emergence of simple and complex cells in visual cortexProceedings of the National Academy of Sciences, 2003