A 50-nm CMOS technology for high-speed, low-power, and RF applications in 100-nm node SoC platform

13 November 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 10.5.1-10.5.4
https://doi.org/10.1109/iedm.2001.979472

Abstract

We have developed 100-nm node CMOS platform mixed with high performance and low-power/RF applications. This platform is featured by an Offset Source/Drain structure for gate length reduction without reducing drive current, and by a SSC (Super Steep Channel) profile for improving low-power/RF performance in terms of carrier mobility and 1/f noise.

Keywords

CMOS TECHNOLOGY
RADIO FREQUENCY
MOSFET CIRCUITS
FABRICATION
ION IMPLANTATION
LOW VOLTAGE
DIELECTRIC DEVICES
LABORATORIES
APPLICATION SPECIFIC INTEGRATED CIRCUITS
CMOS INTEGRATED CIRCUITS

This publication has 1 reference indexed in Scilit:

1/f noise in CMOS transistors for analog applications
IEEE Transactions on Electron Devices, 2001