An ECL 2.8ns 16K RAM with 1.2K logic gate array

• 1 January 1986
• conference paper
• Published by Institute of Electrical and Electronics Engineers (IEEE)
• Vol. XXIX, 256-257
• https://doi.org/10.1109/isscc.1986.1156902

Abstract

Keywords

• LOGIC ARRAYS
• LOGIC GATES
• CAPACITANCE
• CUTOFF FREQUENCY
• RING OSCILLATORS