A Verification Technique for Hardware Designs
- 1 January 1982
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 832-841
- https://doi.org/10.1109/dac.1982.1585591
Abstract
Most existing hardware design verification techniques (logic simulation, symbolic simulation etc.), as well as the design phase, are rather synthetic. This paper discusses an analytic verification technique with examples of its application. This technique employs backward symbolic simuation, or causality tracing, which is carried out from the negation of a proposition which should be verified. Analyticity this technique has, not only makes verification powerful but gives it another feature, design error diagnosis.Keywords
This publication has 3 references indexed in Scilit:
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- A Digital System Design Language (DDL)IEEE Transactions on Computers, 1968