Modified CORDIC algorithm with reduced iterations

20 July 1989

journal article
Published by Institution of Engineering and Technology (IET) in Electronics Letters

Vol. 25 (15) , 950-951
https://doi.org/10.1049/el:19890636

Abstract

In this contribution we present a modified CORDIC algorithm that offers a considerable latency time reduction and chip area savings when compared with the original CORDIC method. The operations used are adds, shifts, and multiplication or division.

Keywords

DIVISION
MULTIPLICATION
CHIP AREA SAVINGS
REDUCED ITERATIONS
ADDS
SHIFTS
LATENCY TIME REDUCTION
MODIFIED CORDIC ALGORITHM

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