A graph-theoretic via minimization algorithm for two-layer printed circuit boards
- 1 May 1983
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Circuits and Systems
- Vol. 30 (5) , 284-299
- https://doi.org/10.1109/tcs.1983.1085357
Abstract
No abstract availableKeywords
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