Parallel channel routing
- 6 January 2003
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 128-133
- https://doi.org/10.1109/dac.1988.14747
Abstract
A parallel algorithm is proposed for solving the problem of channel and switchbox routing in the design of VLSI chips. The algorithm is suitable for implementation on a shared-memory multiprocessor environment. Our approach does not impose restrictions on the channel type (such as fix or variable channel widths) and the number of available layers. The algorithm contains three major phases: 1) dividing the channel into several regions by selecting some columns, 2) assigning tracks to nets of the selected columns, and 3) assigning tracks to nets of the columns in each region.Keywords
This publication has 10 references indexed in Scilit:
- A Mixed HVH-VHV Algorithm for Three-Layer Channel RoutingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987
- General purpose routerPublished by Association for Computing Machinery (ACM) ,1987
- Routing with a scanning window-8Ma unified approachPublished by Association for Computing Machinery (ACM) ,1987
- Two-dimensional router for double layer layoutPublished by Association for Computing Machinery (ACM) ,1985
- Three-Layer Channel RoutingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1984
- Hierarchical Wire RoutingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1983
- River Routing: Methodology and AnalysisPublished by Springer Nature ,1983
- A New Channel Routing AlgorithmPublished by Springer Nature ,1983
- Efficient Algorithms for Channel RoutingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1982
- A “greedy” channel routerPublished by Association for Computing Machinery (ACM) ,1982