Abstract
A novel low-power, high-speed, direct digital synthesizer (DDS) architecture is presented, called the composite DDS (CDDS). A low-speed, high-resolution DDS is combined with a high-speed, low-resolution DDS is combined with a high-speed, low-resolution phase accumulator and phase shifter via the serrodyne modulation technique. The low-speed circuitry provides a fine tuning while the high-speed circuitry provides coarse tuning. By minimizing the amount of circuitry required to clock at high speeds, DC power is conserved. Results from numeric simulations and a low-frequency proof-of-consents breadboard are presented. Progress on an 800-MHz CDDS development effort is described, and proposed enhancements to the CDDS architecture which promise improved performance are discussed.

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