A 10,000 gate bipolar VLSI masterslice utilizing four levels of metal

1 January 1983

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

Vol. XXVI, 152-153
https://doi.org/10.1109/isscc.1983.1156480

Abstract

A family of bipolar gate arrays, containing up to 10,000 logic gates, and utilizing four levels of metal will be described. The family also includes a logic chip containing a customized on-chip array.

Keywords

VERY LARGE SCALE INTEGRATION
WIRES
LOGIC GATES
WIRING
DELAY
SILICON
INTEGRATED CIRCUIT INTERCONNECTIONS
LOGIC DEVICES
BOOKS
LARGE SCALE INTEGRATION

This publication has 3 references indexed in Scilit:

A study on bipolar VLSI gate-arrays assuming four layers of metal
IEEE Journal of Solid-State Circuits, 1982
A 1500 gate, random logic, large-scale integrated (LSI) masterslice
IEEE Journal of Solid-State Circuits, 1979
A 1500-gate random logic LSI masterslice
Published by Institute of Electrical and Electronics Engineers (IEEE) ,1979