Interface effects of SIPOS passivation

1 June 1986

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices

Vol. 33 (6) , 779-787
https://doi.org/10.1109/t-ed.1986.22568

Abstract

Electrical characterization of metal-semi-insulating polycrystalline silicon (SIPOS)-Si samples have been carried out usingIV,C-V, andC-ttechniques. Bulk resistivity and interface properties have been examined. The results indicate that annealing can give rise to a current barrier at the SIPOS-Si interface that constitutes another mechanism for interface charge formation as distinct from interface states. This current barrier-induced interface charge can lead to significant spreading of the depletion zone on test diodes. With SIPOS bulk resistivity greater than 10⁸Ω . cm, the interface electrical properties are shown to have greater influence than bulk SIPOS properties on device behavior.

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