Transistor-transistor logic with high packing density and optimum performance at high inverse gain
- 1 September 1968
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 3 (3) , 261-267
- https://doi.org/10.1109/jssc.1968.1049897
Abstract
The advantages of using thin epitaxial layers for bipolar integrated circuits are discussed in this paper. Using epitaxial layer thicknesses of ~ 1 /spl mu/ and a low-voltage form of transistor-transistor logic, packing densities of 10/SUP 5/ logic gates/in/SUP 2/ have been achieved. The power x delay product of the circuits was 5 pJ. The transistors were formed in 1 /spl mu/ thick epitaxial layers and have inverse common-emitter current gains of 2 to 3. These high inverse gains make practical some new circuit configurations, including a dual-emitter inverter with reduced storage time. The thin epitaxial layer may be p type, rather than the usual n type, and this makes possible a new isolation scheme that allows the fabrication of bipolar integrated circuits using only five photolithographic steps.Keywords
This publication has 1 reference indexed in Scilit:
- Large-Signal Behavior of Junction TransistorsProceedings of the IRE, 1954