A twin-well CMOS process employing high-energy ion implantation

1 April 1986

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices

Vol. 33 (4) , 450-457
https://doi.org/10.1109/T-ED.1986.22511

Abstract

A twin-well CMOS process has been developed using ion implantation with energies up to 1 MeV. The high-energy ion-implantation steps eliminate the need for extended processing times at high temperatures. As a consequence, this permits an increase in packing density, independent control of critical electrical parameters, and simplified processing. The resulting process includes advantages of recent developments in bulk CMOS: an n-type isolation well in a p-p+substrate and retrograde wells. This paper discusses the processing steps involved and provides the resulting device characteristics. An interesting application of the process is also presented, which is the realization of a gate array with TTL-compatible input and output buffers.

Keywords

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