An on-chip back-bias generator for MOS dynamic memory
- 1 October 1980
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 15 (5) , 820-826
- https://doi.org/10.1109/jssc.1980.1051477
Abstract
An on-chip back-bias generator for 64K dynamic MOS RAM has been developed.The use of this generator achieves the goal of a single 5 V power supply part while preserving the advantages of substrate bias in n-channel MOS technology. These advantages include the elimination of substrate injection current from localized forward biasing of diodes, improved speed and power characteristics, and a larger differential data signal on the bit sense lines. The generator circuit avoids several pit-falls on on-chip V/SUB BB/ generation. The circuit pumps to a known regulated voltage. This avoids substrate drift with changes in substrate current resulting from changes in cycle time. This drift will change device characteristics and degrade storage levels. A unique two-level reference scheme avoids changes in substrate bias voltage that otherwise result from the shift in V/SUB BB/ between precharged and active memory states when memory duty cycle changes. The standby power used by the generator is only 0.74 mW.Keywords
This publication has 3 references indexed in Scilit:
- A single 5V 64K dynamic RAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1980
- A 5V-only 64K dynamic RAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1980
- Leakage studies in high-density dynamic MOS memory devicesIEEE Transactions on Electron Devices, 1979