Analysis of Memory Interference in Multiprocessors
- 1 September 1975
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-24 (9) , 897-908
- https://doi.org/10.1109/t-c.1975.224335
Abstract
This paper presents Markov chain models for analyzing the extent of memory interference in multiprocessor systems with a crosspoint switch for processor-memory communication. Processor behavior is simplified to an ordered sequence of a memory request followed by a certain amount of processing time. The results predicted by the model are compared with some simulation results and some actual measurements on C.mmp, a multiprocessor system being built at Carnegie-Mellon University.Keywords
This publication has 3 references indexed in Scilit:
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- Effects of storage contention on system performanceIBM Systems Journal, 1969
- Probability Models for Multiprogramming Computer SystemsJournal of the ACM, 1967