A bit-level pipelined implementation of a CMOS multiplier-accumulator using a new pipelined full-adder cell design

7 January 2003

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 49-53
https://doi.org/10.1109/pccc.1989.37359

Abstract

A bit-level pipelined 12*12-bit two's-complement multiplier with a 27-bit accumulator has been designed for applications in high-speed digital communication systems. A new quasi n-p domino logic structure has been investigated and adopted in this multiplier-accumulator design. When used in fully-pipelined circuits, this logic structure results in a much shorter propagation delay in comparison with conventional CMOS logic, pseudo-NMOS logic, and even standard n-p domino (NORA) logic. The chip complexity is approximately 10000 transistors, and the die area is 9.3 mm/sup 2/ in a 1.25- mu p-well CMOS technology. Based on SPICE simulations using conservative device parameters, the clock speed is projected to be over 150 MHz (i.e. >150 million multiply-accumulate operations per second), and the estimated power-speed ratio is 16 mW/MHz.<>

Keywords

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