Adapting cache line size to application behavior
- 1 May 1999
- proceedings article
- Published by Association for Computing Machinery (ACM)
- p. 145-154
- https://doi.org/10.1145/305138.305188
Abstract
A cache line size has a significant effect on miss rate andmemory traffic. Today's computers use a fixed line size,typically 32B, which may not be optimal for a given application.Optimal size may also change during applicationexecution. This paper describes a cache in whichthe line (fetch) size is continuously adjusted by hardwarebased on observed application accesses to the line.The approach can improve the miss rate, even over theoptimal for the fixed line size, as well as...Keywords
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