CMOS implementation of analog Hebbian synaptic learning circuits

9 December 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

Vol. i, 437-442
https://doi.org/10.1109/ijcnn.1991.155217

Abstract

CMOS VLSI circuits for the implementation of analog Hebbian synapses with in situ learning have been designed, fabricated, and tested. Synaptic weights are stored as analog voltages on integrated linear capacitors located at each synapse. These analog synaptic circuits are more area-efficient than their digital equivalents, resulting in enormous information processing potential. Investigations show that neural network architectures, such as networks using Hebbian and contrastive Hebbian learning, can tolerate highly imperfect analog computational components. These networks can use their learning capability to compensate for component variations, making it possible to implement them using simple, silicon area-efficient circuits. The synaptic circuits described have been incorporated into a fully analog 600-synapse, 28000-transistor neural network to investigate their behavior in a medium-sized system.

Keywords

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