30-circuit monolithic chip with 750-PS loaded-circuit delay per stage

1 January 1969

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

Vol. XII, 72-73
https://doi.org/10.1109/isscc.1969.1154764

Abstract

A high-speed 30-circuit silicon chip using non-saturating emitter-coupled logic circuits with 750-ps loaded delay per stage using 3-level metalization will be described. The chip contains 210 transistors and 196 resistors.

Keywords

DELAY EFFECTS
RESISTORS
SILICON
IMPEDANCE
LATCHES
SWITCHES
INTEGRATED CIRCUIT INTERCONNECTIONS
DH-HEMTS
COUPLING CIRCUITS
LOGIC CIRCUITS