Comparative analysis of different implementations of multiple-input signature analyzers
- 1 January 1988
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. 37 (11) , 1411-1414
- https://doi.org/10.1109/12.8706
Abstract
Signature analysis is an accepted method of obtaining data compression for built-in testing applications. The author deals with a unified approach to the analysis of multiple-input signature analyzers by considering them as finite state switching circuits. This approach is used to investigate and compare different implementations, and it is shown that there is a large range of alternatives to achieve a given characteristic polynomial. Particular emphasis is placed on the two most common implementations. It is shown that both perform polynomial division, with each input of one circuit being equivalent to a combination of inputs of the other. The approach also gives a method of expressing aliasing patterns for both implementations, which leads to a study of the differences with regard to certain error detection capabilities.Keywords
This publication has 8 references indexed in Scilit:
- Analysis and simulation of parallel signature analyzersComputers & Mathematics with Applications, 1987
- Verification Testing—A Pseudoexhaustive Test TechniqueIEEE Transactions on Computers, 1984
- On Random Pattern Test LengthIEEE Transactions on Computers, 1984
- Random-Pattern Coverage Enhancement and Diagnosis for LSSD Logic Self-TestIBM Journal of Research and Development, 1983
- Design for Autonomous TestIEEE Transactions on Computers, 1981
- Measures of the Effectiveness of Fault Signature AnalysisIEEE Transactions on Computers, 1980
- Efficiency of Random Compact TestingIEEE Transactions on Computers, 1978
- An Advanced Fault Isolation System for Digital LogicIEEE Transactions on Computers, 1975