Power distribution modelling of high performance first level computer packages

30 December 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 202-205
https://doi.org/10.1109/epep.1993.394554

Abstract

A methodology for obtaining a model of the power distribution of a computer package is presented. This model is suitable for determining the noise and aiding in the design of a computer package. The physical features of a typical first-level multi-layered computer package is shown. Semiconductor chips and decoupling capacitors are placed on the top surface of the package and the module is connected to a board or card for communication with other components of the computer. A schematic of the final inductance model of a multi-layered ceramic single chip module used in computer products is shown.<>

Keywords

POWER DISTRIBUTION
DISTRIBUTED COMPUTING
HIGH PERFORMANCE COMPUTING
POWER SYSTEM MODELING
SEMICONDUCTOR DEVICE PACKAGING
SOLID MODELING
SEMICONDUCTOR DEVICE NOISE
DESIGN OPTIMIZATION
COMPUTER NETWORKS
POWER SYSTEM RELIABILITY

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