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Test pattern generation for sequential MOS circuits by symbolic fault simulation
Home
Publications
Test pattern generation for sequential MOS circuits by symbolic fault simulation
Test pattern generation for sequential MOS circuits by symbolic fault simulation
KC
K. Cho
K. Cho
RB
R. E. Bryant
R. E. Bryant
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1 January 1989
proceedings article
Published by
Association for Computing Machinery (ACM)
p.
418-423
https://doi.org/10.1145/74382.74452
Abstract
No abstract available
Cited
Cited by 47 articles
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