Dynamic-sleep transistor and body bias for active leakage power control of microprocessors

22 December 2003

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 102-481 vol.1
https://doi.org/10.1109/isscc.2003.1234225

Abstract

Sleep transistors and body bias are used to control active leakage for a 32b integer execution core implemented in a 100nm dual V, CMOS technology. A PMOS sleep transistor degrades performance by 4% but offers 20/spl times/ leakage reduction which is further improved with body bias. Time constants for leakage convergence range from 30ns to 300ns allowing 9-44% power savings for idle periods greater than 100 clock cycles.

Keywords

POWER CONTROL
MICROPROCESSORS
CLOCKS
SLEEP
FREQUENCY
SWITCHES
POWER MEASUREMENT
CMOS TECHNOLOGY
MOS DEVICES
POWER GRIDS

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